1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, to a semiconductor device in which a dielectric film located between electrodes of a capacitor is made of high permittivity dielectric material as well as a method of manufacturing the same.
2. Description of the Related Art
In recent years, demands for semiconductor memory devices have been rapidly increased owing to remarkable spread of information equipments such as computers. In connection with function, such devices have been demanded that have a large scale storage capacity and can operate at a high speed. In compliance with these demands, technologies have been developed for improving degree of integration, responsiveness and reliability of the semiconductor memory devices.
DRAMs (Dynamic Random Access Memories) have been known as a kind of semiconductor memory devices which can perform random input and output of storage information. The DRAM includes a memory cell array, which is a storage region accumulating a large number of storage information, and a peripheral circuitry required for external input and output.
A structure of the DRAM will be described below.
FIG. 33 is a block diagram showing a structure of a conventional DRAM. Referring to FIG. 33, a DRAM 350 includes a memory cell array 351, a row and column address buffer 352, a row decoder 353, a column decoder 354, a sense refresh amplifier 355, a data-in buffer 356, a data-out buffer 357 and a clock generator 358.
Memory cell array 351 serves to accumulate data signals of stored information. Row and column address buffer 352 serves to receive an externally applied address buffer signal used for selecting a memory cell which forms a unit memory circuit. Row decoder 353 and column decoder 354 decode the address buffer signal to designate the memory cell. Sense refresh amplifier 355 serves to amplify and read the signal stored in the designated memory cell. Data-in buffer 356 and data-out buffer 357 serve to input and output data, respectively. Clock generator 358 serves to generate a clock signal.
In the semiconductor chip of the DRAM thus constructed, memory cell array 351 occupies a large area. Memory cell array 351 is formed of a plurality of memory cells which are disposed in a matrix form and each is operable to store the unit storage information. Thus, in general, the memory cell is formed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto. This memory cell is well known as a memory cell of one-transistor and one-capacitor type. The memory cell thus constructed has a simple structure, so that the degree of integration of the memory cell array can be improved readily and thus the memory cells have been widely used in the DRAM of a large capacity.
The memory cell of the DRAM can be classified into several types according to the structure of the capacitor. Among them, in a stacked type capacitor an opposition area of electrodes of the capacitor can be increased readily. Therefore, a sufficient capacitor capacitance can be readily ensured even if elements of the semiconductor device are miniaturized to a high extent for improving the degree of integration. By this reason, the stacked type capacitors have been widely used in accordance with high integration of the semiconductor device.
FIG. 34 shows a sectional structure of a DRAM provided with a stacked type capacitor in the prior art. Referring to FIG. 34, a silicon substrate 331 is provided at its surface with an isolating oxide film 333 for electrically isolating elements from each other. A channel stopper region 335 is formed at a region under isolating oxide film 333. Isolating oxide film 333 and channel stopper region 335 electrically isolate a portion of the surface of silicon substrate 331, at which a memory cell of the DRAM is formed. Memory cell includes one transfer gate transistor 330 and one capacitor 320.
Transfer gate transistor 330 includes a gate oxide film 321, a gate electrode 323 and a pair of source/drain regions 325. Source/drain regions 325 are formed at the surface of silicon substrate 331 with a predetermined space between each other. Source/drain regions 325 have an LDD (Lightly Doped Drain) structure. Thus, each of source/drain regions 325 is formed of a two-layer structure including a relatively lightly doped impurity region 325a and a relatively heavily doped impurity region 325b. Gate electrode 323 is formed on a region located between source/drain regions 325 with gate oxide film 321 therebetween. The surface of gate electrode 323 is covered with an insulating film 327.
There is formed an insulating film 329 which covers transfer gate transistor 330 and partially exposes the surfaces of source/drain regions 325. Capacitor 320 is in contact with one of paired source/drain regions 325 not covered by insulating film 329.
Capacitor 320 has a lower electrode layer 313, a capacitor insulating layer 315 and an upper electrode layer 317. Lower electrode layer (storage node) 313 is in contact with the surface of one of paired source/drain regions 325 and extends over insulating film 329. Capacitor insulating layer 315 mainly made of silicon oxide covers the surface of lower electrode layer 313. Upper electrode layer (cell plate) 317 covers lower electrode layer 313 with capacitor insulating layer 315 therebetween. Electric charges are accumulated in a region at which lower electrode layer 313 and upper electrode layer 317 sandwiching capacitor insulating layer 315 are opposed to each other.
An interlayer insulating film 301 covering capacitor 320 is formed over the whole surface of silicon substrate 331. Interlayer insulating film 301 is provided with a contact hole 301a. Contact hole 301a reaches the surface of the other of source/drain regions 325. A bit line 337 is formed on interlayer insulating film 301 and is in contact with source/drain region 325 through contact hole 301a.
Bit line 337 includes a polysilicon layer 337a and a tungsten silicide layer 337b. More specifically, polysilicon layer 337a and tungsten silicide layer 337b are successively deposited to form bit line 337. Bit line 337 is covered with an insulating film 319.
The memory cell having the stacked type capacitor shown in FIG. 34 is suitable to high integration owing to the structural features described above.
If the DRAM is integrated to a higher extent, further reduction of the memory cell size is inevitably required. In accordance with reduction of the memory cell size, a planar area occupied by the capacitor is also reduced. If the occupied planar area is reduced as described above, an area of surface region of lower electrode layer 313 decreases substantially in proportion to the ratio of planar reduction, and accordingly, the opposition area of electrodes of capacitor 320 also decreases. Thus, the amount of charges accumulated in the capacitor (i.e., the amount of charges accumulated in the memory cell of one bit) decreases. If the amount of charges accumulated in the memory cell of one bit decreases below a predetermined value, operation of the DRAM as the storage region becomes unstable, resulting in reduction of reliability.
In order to prevent instability in operation of DRAM, it is necessary to increase the capacitance of capacitor while maintaining the occupied planar area within a limited value. In order to increase the capacitor capacitance, such measures as (1) reduction of a thickness of the capacitor insulating layer and as (2) increase of the dielectric constant of the capacitor insulating layer have been studied.
In connection with the reduction of the thickness of the capacitor insulating layer at (1) above, the thickness has been generally reduced to a limit as long as a silicon oxide film is used as the capacitor insulating layer. Therefore, it is necessary to provide a capacitor of a complicated form such as a cylindrical form or a fin-like form in order to increase the capacitor capacitance using the capacitor insulating layer made of a silicon oxide film. However, the capacitor having such a complicated form requires an extremely complicated manufacturing process.
Accordingly, technologies are now being developed extensively in connection with increase of the capacitor dielectric constant at (2) above. Increase of the dielectric constant of the capacitor insulating layer can be achieved by employing the capacitor insulating layer made of material having a high dielectric constant, i.e., so-called high permittivity dielectric material. This high permittivity dielectric material generally has a dielectric constant several times to several hundred times as large as that of a silicon oxide film. Therefore, by using the capacitor insulating layer made of the high permittivity dielectric material, the capacitance can be readily increased while maintaining a simple form of the capacitor.
Examples of the material referred to as the high permittivity dielectric material include tantalum oxide (Ta.sub.2 O.sub.5), lead titanate zirconate (PZT), lanthan-lead titanate zirconate (PLZT), strontium titanate (STO), barium titanate (BTO) and ST.
Description will be made on a memory cell structure of the DRAM having the capacitor employing the capacitor insulating layer made of high permittivity dielectric material, with reference to the drawings showing a conventional semiconductor device.
FIG. 35 is a cross section schematically showing a structure of the conventional semiconductor device. Referring to FIG. 35, a plurality of memory cells of a DRAM are formed at a region in a silicon substrate 431 isolated by isolating oxide films 433 and channel stopper regions 435. Each memory cell is a memory cell of one-transistor and one-capacitor type having a transfer gate transistor 430 and a capacitor 410.
Each transfer gate transistor 430 has a gate oxide film 421, a gate electrode 423 and a pair of source/drain regions 425. Source/drain regions 425 are formed at the surface of silicon substrate 431 with a predetermined space between each other. Source/drain regions 425 have an LDD (Lightly Doped Drain) structure. Thus, each of source/drain regions 425 is formed of a two-layer structure including a relatively lightly doped impurity region 425a and a relatively heavily doped impurity region 425b. Gate electrode 423 is formed on a region located between paired source/drain regions 425 with gate oxide film 421 therebetween. The surface of gate electrode 423 is covered with an insulating film 427.
A bit line 437 extends on insulating film 427 and is in contact with one of the paired source/drain regions 425 forming the transfer gate transistor 430. Bit line 437 and transfer gate transistor 430 are covered with an interlayer insulating film 441 formed on the whole surface of silicon substrate 431. Bit line 437 thus covered with interlayer insulating film 441 is in the form of a buried bit line.
Interlayer insulating film 441 is provided with a contact hole 441a. Contact hole 441a reaches a surface of the other of paired source/drain regions 425. Contact hole 441a is filled with a plug layer 443a. Plug layer 443a is made of polysilicon doped with impurity (which will also be referred to as "doped polysilicon"). Capacitor 410 is formed such that it electrically connects to source/drain region 425 via plug layer 443a.
Capacitor 410 has a lower electrode layer 401, a capacitor insulating layer 403 and an upper electrode layer 405. Capacitor insulating layer 403 of capacitor 410 is made of the high permittivity dielectric material such as PZT, as already described. The PZT and PLZT exhibit the largest dielectric constant when layers of them are formed on platinum (Pt). Therefore, lower electrode layer 401 is made of platinum in many cases.
Lower electrode layer 401 is electrically connected to plug layer 443a via barrier layer 413 and extends on the surface of interlayer insulating film 401. Barrier layer 413 prevents diffusion of impurity contained in plug layer 443a into lower electrode layer 401, and also serves to improve adhesion between interlayer insulating film 441 and lower electrode layer 401. Capacitor insulating layer 403 made of high permittivity dielectric material such as PZT covers the surface of lower electrode layer 401. Upper electrode layer 405 covers lower electrode layer 401 with capacitor insulating layer 403 therebetween. Capacitor 410 is covered with an insulating film 445.
Now, a method of manufacturing the conventional semiconductor device described above will be described below.
FIGS. 36 to 45 are schematic cross sections showing a process of manufacturing the conventional semiconductor device in accordance with the order of steps. Referring first to FIG. 36, isolating oxide film 433 is formed at the surface of silicon substrate 431 by, for example, an LOCOS (Local Oxidation of Silicon) method. At this step, channel stopper region 435 is formed at a region under the isolating oxide film 433.
A gate electrodes 423 is formed on the surface of silicon substrate 431 with gate oxide film 421 therebetween. Using gate electrode 423 as a mask, ion implantation is carried out to form relatively lightly doped impurity region 425. Insulating film 427 is formed to cover gate electrode 423. Using insulating film 427 as a mask, ion implantation is carried out to form relatively heavily doped impurity regions 425b. Lightly and heavily doped impurity regions 425a and 425b form source/drain regions 425. In this manner, transfer gate transistor 430 is formed.
Buried bit line 437 is formed such that it extends on insulating films 427 and is in contact with one of source/drain regions 425. A silicon oxide film 441b is formed on the whole surface of silicon substrate 431, for example, by a CVD (Chemical Vapor Deposition) method so that it covers buried bit line 437 and transfer gate transistor 430. A resist film 441c for forming a flat surface is formed on the surface of silicon oxide film 441b. Resist film 441c may be formed by applying an SOG (Spin On Glass) film. Then, resist film 441c and silicon oxide film 441b are etched back up to a position indicated by dotted line.
Referring to FIG. 37, this etchback completes silicon oxide film 441 having a substantially flat surface.
Referring to FIG. 38, photoresist 451 is applied to the whole surface of silicon oxide film 441, and is patterned into an intended configuration, for example, by exposure. This patterning completes resist pattern 451 having hole patterns 451 located above source/drain regions 451. Using this resist pattern 451 as a mask, anisotropic etching is effected on silicon oxide film 441. By this etching, contact hole 441a is formed, which partially exposes the surfaces of source/drain regions 425, in silicon oxide film 441. Thereafter, resist pattern 451 is removed.
Referring to FIG. 39, doped polysilicon film 443 having a film thickness of from 500 to 8000 .ANG. and filling contact hole 441a is formed by the CVD method on the whole surface of silicon oxide film 441. Etchback is effected on doped polysilicon film 443 to expose at least the surface of silicon oxide film 441.
Referring to FIG. 40, the above etchback is carried out such that about 20% to 30% of the film thickness of doped polysilicon film 443 is over-etched for completely removing etching residue on the surface of silicon oxide film 441. This etchback completes plug layer 443a filling contact hole 441a in interlayer insulating film 441.
Referring to FIG. 41, barrier layer 413, which is made of Ti (titanium), TiN (titanium nitride) and Ti (titanium) layers and is in contact with the top surfaces of plug layers 443a, is formed on the whole surface of interlayer insulating film 441. Platinum layer 401 is formed on the whole surface of barrier layer 413 by the sputtering method on the whole surface of barrier layer 413.
Referring to FIG. 42, resist patterns 453 patterned into intended configurations are formed on a part of the surface of platinum layer 401. Using resist pattern 453 as a mask, platinum layer 401 and barrier layer 413 are successively etched and removed. Thereby, lower electrode layers 401 made of platinum are completed. Thereafter, resist pattern 453 is removed by ashing with oxygen plasma.
Referring to FIG. 43, this ashing exposes the top surface of lower electrode layer 401.
Referring to FIG. 44, a sputtering method is performed to form capacitor insulating layer 403 which is made of high permittivity dielectric material such as PZT and covers the surfaces of lower electrode layer 401.
Capacitor insulating film 403 made of, e.g., PZT is generally formed by the sputtering method, but may be formed by the CVD method.
Referring to FIG. 45, upper electrode layer 405 made of, e.g., platinum is formed by the sputtering method to cover lower electrode layer 401 with capacitor insulating layer 403 made of high permittivity dielectric material therebetween. Thereby, capacitor 401 including lower electrode layer 401, capacitor insulating layer 403 and upper electrode layer 405 is completed. Insulating film 445 covering capacitor 410 is formed by the CVD method.
In the above manufacturing process, the CVD method may be employed instead of the sputtering method for forming capacitor insulating layer 403 at the process shown in FIG. 45, in which case the semiconductor device shown in FIG. 46 is completed. Referring to FIG. 46, capacitor insulating layer 403 formed by the CVD method is superior in step coverage to the film or layer formed by the sputtering method.
The conventional semiconductor device using the capacitor insulating layer made of high permittivity dielectric material is constructed and manufactured as described above. Further, the capacitor capacitance can be readily increased while maintaining a simple shape of the capacitor as described above, so that such a capacitor is a promising candidate for highly integrated storage element such as 256M DRAM.
However, according to the conventional semiconductor device and the manufacturing method, capacitor insulating layer 403 is formed after patterning of lower electrode layer 401. This results in degradation of characteristics relating to the breakdown voltage between upper and lower electrode layers forming capacitor 410 as well as degradation of characteristics relating to a resistance against leak between them. This disadvantage will be described below in connection with the cases where capacitor insulating layer 403 is formed (1) by the sputtering method and (2) the CVD method.
(1) In the case of the sputtering method
(i) Referring to FIG. 45, lower electrode layer 401 is formed on interlayer insulating film 441 by patterning the same into an intended configuration. Therefore, a step is formed between the top surface of lower electrode layer 401 and the top surface of interlayer insulating film 441. Capacitor insulating film 403 is formed on the surface including the step by a method such as a sputtering method of which step coverage is poor. Therefore, capacitor insulating layer 403 becomes thin at a lower end of the stepped portion (indicated at "S"). If capacitor insulating layer 403 becomes thin, a leak current flows through this thin portion indicated at "S" between lower electrode layer 401 and upper electrode layer 405 however small this portion may be, so that it is difficult to ensure a predetermined breakdown voltage. Thus, it is impossible to obtain good anti-leak characteristics and good breakdown voltage characteristics.
(ii) Referring to FIG. 47, if capacitor insulating layer 403 is formed after the patterning of lower electrode layer 401, capacitor insulating layer 403 is in contact with lower electrode layer 401 and interlayer insulating film 441. Thus, capacitor insulating layer 403 has a portion 403a, which is in contact with and located on lower electrode layer 401 made of platinum, and a portion 403b, which is in contact with and located on interlayer insulating film 441.
In general, it has been known that perovskite structures cannot be readily obtained in a layer of high permittivity dielectric material containing lead such as PZT or PLZT, if the layer is formed on a silicon oxide film, and the perovskite structures can be readily obtained, if it is formed on a platinum film.
The inventors of the instant invention have conducted an experiment to find that PZT and PLZT can achieve better anti-leak characteristics as they contain more perovskite structures. The method and result of the experiment will be described below.
Samples (A) and (B) shown in FIG. 48 were prepared.
FIG. 48 is a schematic cross section showing a structure of the sample. Referring to FIG. 48, a sample 510 includes a silicon substrate 501, and also includes a silicon oxide film (SiO.sub.2) 503, a platinum (Pt) layer 505, a film 507 made of high permittivity dielectric material (which will be referred to as a "high permittivity dielectric material film" hereinafter) and a patterned platinum layer 509, which are successively deposited on silicon substrate 501. High permittivity dielectric material film 507 has a two-layer structure including PZT and PbTiO.sub.3 layers. The upper layer of PZT has a film thickness of 150 nm and the lower layer of PbTiO.sub.3 has a film thickness of 4 nm.
The sample (A) includes the lower layer made of PbTiO.sub.3 which was formed in an atmosphere containing Ti (titanium) at a flow rate of 60 sccm. The sample (B) includes the lower layer made of PbTiO.sub.3 which was formed in an atmosphere containing Ti (titanium) at a flow rate of 180 sccm.
FIG. 49 shows surface conditions of high permittivity dielectric material films 507 of the samples (A) and (B) observed with a scanning electron microscope (SEM). Referring to FIG. 49, white portions in the surfaces of high permittivity dielectric material films 507 represent the perovskite structures. The white portions (perovskite structures) are coarsely distributed in the sample (A), while they are densely distributed in the sample (B). Thus, the sample (B) has more perovskite structures than the sample (A). This was confirmed with the following X-ray diffraction.
In FIG. 50A and FIG. 50B show peak intensity ratios obtained by X-ray diffraction of the two samples (A) and (B), respectively. Referring to FIG. 50A and FIG. 50B abscissa gives the angle of diffraction, and the ordinate gives the intensity. In the sample (A) (in FIG. 50A), the peak intensity around 30 degrees representing the perovskite structures is small as compared with the peak intensity around 35 degrees corresponding to the structures other than the perovskite structure. Meanwhile, in the sample (B) in FIG. 50B), the peak intensity around 30 degrees representing the perovskite structures is large as compared with the peak intensity around 35 degrees corresponding to the structures other than the perovskite structure. Thus, it is confirmed that the sample (B) has more perovskite structures than the sample (A).
For the samples (A) and (B) prepared in this way, leak currents were measured. The measurement was carried in such a manner that a voltage was applied to patterned platinum layer 509 in FIG. 48, and a current value flowing through high permittivity dielectric material film 507 at that time was measured.
FIG. 51 shows the leak current values of the samples (A) and (B) measured by the above manner. Referring to FIG. 51, abscissa gives the voltage applied to patterned platinum layer 509, and ordinate gives the density (so-called leak current density) of current flowing through high permittivity dielectric material film 507. As can be seen from FIG. 51, it was found that the leak current of sample (A) was higher than that of sample (B) if the equal voltage was applied to the samples (A) and (B).
From the aforementioned results of experiment, it is found that the sample (B) having more perovskite structures generates less leak current than the sample (A) having fewer perovskite structures, and thus has better anti-leak characteristics.
By the above reason, portion 403a of capacitor insulating layer 403 formed on platinum layer 401 in FIG. 47 has better anti-leak characteristics because it has a relatively large number of perovskite structures. Meanwhile, portion 403b formed on interlayer insulating film 441 cannot have good anti-leak characteristics because it has a relatively small number of perovskite structures. Therefore, in the state where electric charges are accumulated in lower electrode layer 401 and upper electrode layer 405 and a voltage is applied to capacitor insulating layer 403, a leak path between electrodes 401 and 405 through which a leak current flows, for example, as indicated by arrow A in the figure, is likely to be formed at portion 403b formed on interlayer insulating film 441. Therefore, capacitor 410 cannot obtain good anti-leak characteristics and good breakdown voltage characteristics.
As can be understood from (i) and (ii) above, capacitor 410 in the prior art cannot have good anti-leak characteristics and good breakdown voltage characteristics if the capacitor insulating layer 403 is formed by the sputtering method.
(2) In the case of the CVD method
Referring to FIGS. 42 and 43, according to the conventional method of manufacturing the semiconductor device, resist pattern 453 is removed by ashing with oxygen plasma after the patterning of lower electrode layer 401. In this ashing step, portions 461 formed at the top surface of lower electrode layer 401 are damaged and contaminated by the oxygen plasma as shown in FIG. 52.
Referring to FIG. 42, resist pattern 453 is generally made of organic material and contains carbon, hydrocarbon or the like. Therefore, if resist pattern 453 is formed on lower electrode layer 401, lower electrode layer 401 absorbs carbon, hydrocarbon or the like at its surface. Therefore, it is difficult to remove completely carbon, hydrocarbon or the like at lower electrode layer 401 even if resist pattern 453 is removed by ashing. Consequently, absorbed substance 463 such as carbon and hydrocarbon remains partially at the top surface of lower electrode layer 401 shown in FIG. 52.
The capacitor insulating layer is formed by the CVD method while leaving damaged portions 461 and absorbed substance 463 at the lower electrode layer 401 as described above. The film formation by the CVD method is very sensitive to the surface state of the base film. Therefore, if the capacitor insulating layer is formed at the damaged and/or contaminated platinum surface by the CVD method, capacitor insulating layer 403 contains fewer perovskite structures than that formed on a pure platinum surface. Due to the fact that capacitor insulating layer 403 contains few perovskite structures, generation of the leak current is likely by the same reasons as above, and thus it is difficult to ensure the predetermined breakdown voltage between electrodes 401 and 405. Thus, good anti-leak characteristics and breakdown voltage characteristics cannot be obtained between lower and upper electrode layers 401 and 405.
By the above reasons, it is impossible to obtain capacitor 410 having good anti-leak characteristics and good breakdown voltage characteristics in the prior art, if capacitor insulating layer 403 is formed by the CVD method.